1. Field of the Invention
The present invention generally relates to semiconductor technology. More particularly, the present invention relates to a tapered through silicon via stacked structure and a method of manufacturing the same.
2. Description of the Prior Art
In conventional semiconductor chips, ICs are formed on the active surfaces of the semiconductor chips or substrates with conventional electrical terminals, such as bonding pads formed on the active surfaces. In high-density electrical interconnections, 3D chip stacking was developed with electrical terminals not only disposed on the active surfaces but also on the corresponding back surfaces of the semiconductor chips. Through silicon via (TSV) is the technology that enables the vertical stacking of several chips or wafers to assemble 3D chip stacking packages/modules or wafer bonding with high power, high densities, and small dimensions. The TSVs are electrically-conductive through holes inside a chip that penetrate through the top surface and the bottom surface of a chip to create vertical electrical connections without any interposers nor bonding wires. The TSVs provide direct vertical electrical connections that do not go through the sidewalls at the edges of the chips, so as to shorten the electrical paths. The TSVs can further enhance the integration and the performances of an electronic device through greatly reducing the packaging heights and dimensions, in order to increase the speed, and to decrease the power consumption of the electronic device.
In order to connect the TSVs of stacked chips, the TSVs on each chip should be correspondingly aligned to each other. With the trend in the industry towards scaling down the size of circuit structures, the size of the TSV connections is also getting smaller and smaller. Thus, it becomes more difficult to accurately align every TSV on one chip or substrate to the corresponding TSV on another chip or substrate.
In U.S. Pat. No. 6,908,785 Kim discloses a semiconductor chip with TSV structures. In this structure, each semiconductor chip is provided with a plurality of through holes penetrating therethrough. The conductive metals are disposed around each through hole and connected to electrical terminals or circuits on both surfaces of the semiconductor chip. The through holes with conductive metals disposed therearound serve as the TSV structure of this invention. The invention is featured with a plurality of conductive pins pre-disposed on a carrier as vertical electrical connections between the vertically stacked semiconductor chips. However, in order to electrically connect all the semiconductor chips to the carrier, all the conductive pins have to be straight without any bending, deformation, nor shifting and should be accurately aligned and inserted into all corresponding through holes. Once one of the conductive pins or the semiconductor chips is bent, deformed or shifted during the stacking processes, the conductive pins can not be easily inserted into the through holes of the semiconductor chips stacked afterwards. This leads to alignment issues and poor production yields.
In U.S. Pat. No. 7,838,967 Chen discloses a semiconductor chip having TSV structure. The chip is provided with a plurality of bonding pads disposed respectively on both surfaces of the semiconductor substrate with through holes penetrating therethrough. The invention features an extruded ring protruding from each bonding pad. The extruded ring has two proper dimensions which match each other. In stacking processes, the smaller extruded ring of a bonding pad on one substrate is embedded into and encircled by a larger extruded ring of a bonding pad on another substrate. Accordingly, a plurality of semiconductor chips can be stacked to each other with an accurate alignment process. However, using the extruded ring which protrudes from the bonding pad to connect the chips may inevitably increase the assembly height. Also, in the actual stacking practice, it is difficult for a plurality of annular extruded rings with exactly corresponding dimension to be fit in and connected to each other.
Accordingly, an improved TSV stacked structure is still needed in the industry to facilitate the accuracy of the alignment process of stacked chips or substrates, and to improve the connection quality between the TSV structures.